The inventive concept relates generally to nonvolatile memory devices and methods of fabricating and testing same.
Conventionally, a memory system including a plurality of nonvolatile memory chips (e.g., a solid state drive (SSD)) has been configured in such a way that each of the nonvolatile memory chips includes a peripheral circuit, such as a power circuit. In case where a power chip provided on a system board is used to replace the power circuits of the individual nonvolatile memory chips, it is possible to reduce an area for the power circuit in each nonvolatile memory chip. In addition, it is possible to reduce power consumption.
For example, as disclosed in Japanese Patent Publication No. 2009-3991 and in Ishida et al., A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD, pp. 238-39, IEEE International Solid State Circuits Conf., ISSCC 2009, Digest of Technical Papers, San Francisco, Calif., USA (8-12 Feb. 2009), a memory system may be provided as a multi-chip package in which a plurality of nonvolatile memory chips lacking a power circuit, and a power (or master) chip having a power circuit are stacked one over the other. In this configuration, the power chip is provided on a system board and is used as a common circuit. The power chip and the plurality of the nonvolatile memory chips are connected using through-silicon-vias (TSV) and bonding wires.
In the case of the memory system disclosed in Japan Patent Publication No. 2009-3991 and the Ishida's article, the nonvolatile memory chips are configured without a power circuit, but this leads to certain technical difficulties in the testing of the nonvolatile memory chips. For example, in order to execute certain test processes, the nonvolatile memory chips must be connected to the power chip by an external tester in order to obtain the required operating voltage(s) necessary for testing. Alternately, each nonvolatile memory chip must be at least partially packaged before testing can be performed.
Since the provision of certain high voltages and complicated control timing is usually needed to test nonvolatile memories, such as NAND flash memories, very expensive testing apparatuses are required and difficult, time consuming testing is required. This drives up manufacturing costs.
In addition, where testing is performed only after packaging of the nonvolatile memory chips, or even final packaging of the memory system, a single “bad” nonvolatile memory chip will cause the memory system to fail. This also drives up manufacturing costs.